Block Based Fetch Engine for Superscalar Processors

The implementation of modern high performance computer is increasingly directed toward parallelism in the hardware. However, most of the current fetch units are limited to one branch prediction per cycle and therefore, can fetch no more than one basic block per cycle. While fetching a single basic block each cycle is sufficient for implementations that issue small number of instructions per cycle, it is not for processors with higher peak issue rates. In this paper we proposed a new architecture, which combine the enhanced branch target buffer with the block cache to fetch multiple blocks. The enhanced branch target buffer enhanced the capability of traditional branch target buffer to store multiple branch targets. Block cache keeps the instruction streams that collected at commit stage as blocks. These blocks are renamed and the renamed index is stored in the enhanced branch target buffer as the basic fetching unit. The proposed architecture has been simulated using SimpleScalar 2.0 simulator. The results show that the average instruction fetch pet cycle reaches 4.84 instructions, the average instruction issued per cycle is 3.44 instructions and the average IPC is 2.07. As compare to the baseline machine, we got 87%, 84%, and 56% increase respectively.